As a nonvolatile latch circuit using a ferroelectric capacitor, a 6T2C-type nonvolatile latch circuit using 6 transistors and 2 capacitors (see, for example, Patent Document 1) and a 6T4C-type nonvolatile latch circuit using 6 transistors and 4 capacitors (see, for example, Patent Document 2) are known.
Further, a semiconductor memory that has: a memory cell having a capacitor that stores charges according to the logic of data; a bit line connected to the memory cell; a charge transfer circuit connected to the bit line; a charge storage circuit that is connected to the bit line via the charge transfer circuit, stores charges read from the memory cell to the bit line during read operation, and generates a read voltage according to the stored charges; and a read circuit that generates the logic of data held in the memory cell according to the read voltage generated by the charge storage circuit is known (see, for example, Patent Document 3).
Further, a semiconductor memory having a sense amplifier system that detects and amplifies a potential variation in a pair of bit lines generated by a memory cell of a ferroelectric capacitor is known (see, for example, Patent Document 4).
Further, a ferroelectric memory having a plurality of normal memory cells having ferroelectric capacitors that store data supplied from the outside respectively, a second memory cell having a ferroelectric capacitor that stores inversion data of first data stored in a first memory cell among the normal memory cells, and bit lines connected to the normal memory cells and the second memory cell respectively is known (see, for example, Patent Document 5).
Patent Document 1: U.S. Pat. No. 6,141,237
Patent Document 2: Japanese Laid-open Patent Publication No. 2004-87003
Patent Document 3: Japanese Laid-open Patent Publication No. 2008-234829
Patent Document 4: Japanese Examined Patent Application Publication No. 8-8339
Patent Document 5: International Publication Pamphlet No. WO 2004/107350